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?2016 fairchild semiconductor corporation 1 www.fairchildsemi.com FNB33060T rev. 1.1 march 2016 FNB33060T motion spm 3 ? series FNB33060Tmotion spm ? 3 series features 600 v - 30 a 3-phase igbt inverter with integral gate drivers and protection low-loss, short-circuit rated igbts very low thermal resistance using al 2 o 3 dbc substrate built-in bootstrap diodes and dedicated vs pins simplify pcb layout separate open-emitter pins from low-side igbts for three-phase current sensing single-grounded power supply lvic temperature-sensing built-in for temperature monitoring isolation rating: 2500 v rms / 1 min. applications motion control - home appliance / industrial motor related resources an-9088 - motion spm ? 3 v6 series users guide an-9086 - spm 3 package mounting guide general description FNB33060T is an advanced motion spm ? 3 module providing a fully-featured, high-performance inverter output stage for ac induction, bldc, and pmsm motors. these modules integr ate optimized gate drive of the built-in igbts to minimize emi and losses, while also providing multiple on-module protection features includ- ing under-voltage lockouts, over-current shutdown, thermal monitoring of drive ic, and fault reporting. the built-in, high-speed hvic r equires only a single supply voltage and translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal igbts. separate negative igbt terminals are available for each phase to support the widest variety of control algorithms. package marking and ordering inform ation figure 1. 3d package drawing (click to activate 3d content) device device marking package packing type quantity FNB33060T FNB33060T spm27-ra rail 10
?2016 fairchild semiconductor corporation 2 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series integrated power functions 600 v - 30 a igbt inverter for three-phase dc / ac power conversion (please refer to figure 3) integrated drive, protectio n and system control functions for inverter high-side igbts: gate drive circ uit, high-voltage isolated high-speed level shifting control circuit under-voltage lock-out protection (uvlo) note: available bootstrap circuit exam ple is given in figures 5 and 15. for inverter low-side igbts: gate driv e circuit, short-circuit protection (scp) control supply circuit under-voltage lock-out protection (uvlo) fault signaling: corresponding to uvlo (low-side supply) and sc faults input interface: active-high interface, wor ks with 3.3 / 5 v logic, schmitt-trigger input pin configuration figure 2. top view
?2016 fairchild semiconductor corporation 3 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series pin descriptions pin number pin name pin description 1v dd(l) low-side common bias voltage for ic and igbts driving 2 com common supply ground 3i n (ul) signal input for low-side u-phase 4i n (vl) signal input for low-side v-phase 5i n (wl) signal input for low-side w-phase 6v fo fault output 7v ts output for lvic temperature sensing voltage output 8c sc shut down input for short-circuit current detection input 9i n (uh) signal input for high-side u-phase 10 v dd(h) high-side common bias voltage for ic and igbts driving 11 v b(u) high-side bias voltage for u-phase igbt driving 12 v s(u) high-side bias voltage ground for u-phase igbt driving 13 in (vh) signal input for high-side v-phase 14 v dd(h) high-side common bias voltage for ic and igbts driving 15 v b(v) high-side bias voltage for v-phase igbt driving 16 v s(v) high-side bias voltage ground for v phase igbt driving 17 in (wh) signal input for high-side w-phase 18 v dd(h) high-side common bias voltage for ic and igbts driving 19 v b(w) high-side bias voltage for w-phase igbt driving 20 v s(w) high-side bias voltage ground for w-phase igbt driving 21 n u negative dc-link input for u-phase 22 n v negative dc-link input for v-phase 23 n w negative dc-link input for w-phase 24 u output for u-phase 25 v output for v-phase 26 w output for w-phase 27 p positive dc-link input
?2016 fairchild semiconductor corporation 4 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series internal equivalent circ uit and input/output pins figure 3. internal block diagram notes: 1. inverter low-side is composed of three igbts, freewheeling diodes for each igbt, and one contro l ic. it has gate drive and p rotection functions. 2. inverter power side is composed of four inverter dc-link input terminals and three inverter outp ut terminals. 3. inverter high-side is composed of three igbts, freewheeling diodes, and three drive ics for each i gbt. com v dd in in in v fo v ts c sc out out out n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w) (19) v b(w) (16) v s(v) (15) v b(v) (8) c sc (7) v ts (6) v fo (5) in (wl) (4) in (vl) (3) in (ul) (2) com (1) v dd(l) v dd v b out com v s in v b v s out in com v dd v dd v b out com v s in (18) v dd(h) (17) in (wh) (14) v dd(h) (13) in (vh) (12) v s(u) (11) v b(u) (10) v dd(h) (9) in (uh)
?2016 fairchild semiconductor corporation 5 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series absolute maximum ratings (t j = 25c, unless otherwise specified) inverter part control part bootstrap diode part total system thermal resistance note: 4. these values had been made an acquisition by the calculation considered to des ign factor. 5. for the measurement point of case temperature (t c ), please refer to figure 2. symbol parameter conditions rating unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces collector - emitter voltage 600 v i c each igbt collector current t c = 25c, t j ?? 150c (note 4) 30 a i cp each igbt collector current (peak) t c = 25c, t j ? 150c, under 1 ms pulse width (note 4) 60 a p c collector dissipation t c = 25c per one chip (note 4) 89 w t j operating junction temperature -40 ~ 150 c symbol parameter conditions rating unit v dd control supply voltage applied between v dd(h) , v dd(l) - com 20 v v bs high-side control bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v v in input signal voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com -0.3 ~ v dd +0.3 v v fo fault output supply voltage applied between v fo - com -0.3 ~ v dd +0.3 v i fo fault output current sink current at v fo pin 2 ma v sc current sensing input voltage applied between c sc - com -0.3 ~ v dd +0.3 v symbol parameter conditions rating unit v rrm maximum repetitive reverse voltage 600 v i f forward current t c = 25c, t j ?? 150c (note 4) 0.5 a i fp forward current (peak) t c = 25c, t j ? 150c, under 1 ms pulse width (note 4) 2.0 a t j operating junction temperature -40 ~ 150 c symbol parameter conditions rating unit v pn(prot) self protection supply voltage limit (short circuit protection capability) v dd = v bs = 13.5 ~ 16.5 v, t j = 150c, non-repetitive, < 2 ? s 400 v t c module case operation temperature see figure 2 -40 ~ 125 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinuso idal, ac 1 minute, connection pins to heat sink plate 2500 v rms symbol parameter conditions min. typ. max. unit r th(j-c)q junction to case thermal resistance (note 5) inverter igbt part (per 1 / 6 module) - - 1.4 c / w r th(j-c)f inverter fwd part (per 1 / 6 module) - - 2.4 c / w
?2016 fairchild semiconductor corporation 6 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series electrical characteristics (t j = 25c, unless otherwise specified) inverter part note: 6. t on and t off include the propagation delay time of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the given gate driving condition internally. for the detailed information, please see figure 4 . figure 4. switching time definition symbol parameter conditions min. typ. max. unit v ce(sat) collector - emitter saturation voltage v dd = v bs = 15 v v in = 5 v i c = 30 a, t j = 25c - 1.6 2.2 v v f fwdi forward voltage v in = 0 v i f = 30 a, t j = 25c - 2.0 2.6 v hs t on switching times v pn = 300 v, v dd = 15 v, i c = 30 a t j = 25c v in = 0 v ? 5 v, inductive load see figure 5 (note 6) 0.50 0.90 1.40 ? s t c(on) -0 . 2 00 . 6 0 ? s t off -0 . 8 51 . 3 5 ? s t c(off) -0 . 1 50 . 4 5 ? s t rr -0 . 0 8- ? s ls t on v pn = 300 v, v dd = 15 v, i c = 30 a t j = 25c v in = 0 v ? 5 v, inductive load see figure 5 (note 6) 0.40 0.80 1.30 ? s t c(on) -0 . 2 50 . 6 0 ? s t off -0 . 9 01 . 4 0 ? s t c(off) -0 . 1 50 . 4 5 ? s t rr -0 . 1 0- ? s i ces collector - emitter leakage current v ce = v ces --5m a v ce i c v in t on t c(on) v in(on) 10% i c 10% v ce 90% i c 100% i c t rr 100% i c v ce i c v in t off t c(off) v in(off) 10% v ce 10% i c (a) turn-on (b) turn-off
?2016 fairchild semiconductor corporation 7 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series figure 5. example circuit for switching test figure 6. switching loss characteristics figure 7. temperature profile of v ts (typical) one-leg diagram of spm 3 p n u,v,w v dd (h) in(h) com(h) vb out(h) vs v dd (l) in(l) com(l) out(l) csc tsu vfo i c v pn u,v,w inductor hs switching ls switching v 300v v v +15v +5v 4.7k ? c bs hs switching ls switching v in 0v 5v v dd 0 5 10 15 20 25 30 0 200 400 600 800 1000 1200 1400 1600 1800 2000 switching loss e sw [uj] collector current, i c [amperes] igbt turn-on, eon igbt turn-off, eoff frd turn-off, erec inductive load, v pn = 300v, v dd =15v, t j =25 0 5 10 15 20 25 30 0 200 400 600 800 1000 1200 1400 1600 1800 2000 inductive load, v pn = 300v, v dd =15v, t j =150 switching loss e sw [uj] collector current, i c [amperes] igbt turn-on, eon igbt turn-off, eoff frd turn-off, erec
?2016 fairchild semiconductor corporation 8 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series bootstrap diode part control part note: 7. short-circuit current protection is functioning only at the low-sides. 8. t lvic is the temperature of lvic itself. v ts is only for sensing temperature of lvic and can not shutdown igbts automatically. symbol parameter conditions min. typ. max. unit v f forward voltage i f = 0.1 a, t j = 25c - 2.5 - v t rr reverse recovery time i f = 0.1 a, di f / dt = 50 a / ? s, t j = 25c - 80 - ns symbol parameter conditions min. typ. max. unit i qddh quiescent v dd supply current v dd(h) = 15 v, in (uh,vh,wh) = 0 v v dd(h) - com - - 0.50 ma i qddl v dd(l) = 15 v, in (ul,vl, wl) = 0 v v dd(l) - com - - 6.00 ma i pddh operating v dd supply current v dd(h) = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for high- side v dd(h) - com - - 0.50 ma i pddl v dd(l) = 15v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for low- side v dd(l) - com - - 10.0 ma i qbs quiescent v bs supply current v bs = 15 v, in (uh, vh, wh) = 0 v v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) --0 . 3 0m a i pbs operating v bs supply current v dd = v bs = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for high-side v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) --4 . 5 0m a v foh fault output voltage v dd = 15 v, v sc = 0 v, v fo circuit: 4.7 k ? to 5 v pull-up 4.5 - - v v fol v dd = 15 v, v sc = 1 v, v fo circuit: 4.7 k ? to 5 v pull-up --0 . 5v v sc(ref) short circuit trip level v dd = 15 v (note 7) c sc - com (l) 0.45 0.50 0.55 v uv ddd supply circuit under- voltage protection detection level 9.8 - 13.3 v uv ddr reset level 10.3 - 13.8 v uv bsd detection level 9.0 - 12.5 v uv bsr reset level 9.5 - 13.0 v t fod fault-out pulse width 50 - - ? s v ts lvic temperature sensing voltage output v dd(l) = 15 v, t lvic = 25c (note 8) see figure 7 540 640 740 mv v in(on) on threshold voltage applied between in (uh, vh, wh) - com, in (ul, vl, wl) - com --2 . 6v v in(off) off threshold voltage 0.8 - - v
?2016 fairchild semiconductor corporation 9 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series recommended oper ating conditions note: 9. this product might not make response if input pulse width is less than the recommanded value. figure 8. allowable maximum output current note: 10. this allowable output current value is the reference data for the safe operation of this product. this may be d ifferent fro m the actual application and operating condition. symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p - n u , n v , n w - 300 400 v v dd control supply voltage applied between v dd(h) - com, v dd(l) - com 14.0 15 16.5 v v bs high-side bias voltage applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.0 15 18.5 v dv dd / dt, dv bs / dt control supply variation - 1 - 1 v / ? s t dead blanking time for preventing arm - short for each input signal 1.0 - - ? s f pwm pwm input signal -40 ? c ?? t c ?? 125c, -40 ? c ?? t j ?? 150c - - 20 khz v sen voltage for current sensing applied between n u , n v , n w - com (including surge voltage) - 5 5 v pw in(on) minimum input pulse width v dd = v bs = 15 v, i c ?? 60 a, wiring inductance between n u, v, w and dc link n < 10nh (note 9) 2.0 - - ? s pw in(off) 2.0 - - t j junction temperature - 40 - 150 ? c 0 20 40 60 80 100 120 140 0 5 10 15 20 25 v dc = 300 v, v dd = v bs = 15 v t j = 150 , t c = 125 m.i. = 0.9, p.f. = 0.8 sinusoidal pwm f sw = 15 khz f sw = 5 khz allowable output current, i orms [a rms ] case temperature, t c [ ]
?2016 fairchild semiconductor corporation 10 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series mechanical characteristics and ratings figure 9. flatness measurement position figure 10. mounting screws torque order note: 11. do not make over torque when mounting screws. much mounting torque may cause dbc cracks, as well as bolts and al heat-sink destruction. 12. avoid one-sided tightening stress. figure 10 shows the recommended torque order for mounti ng screws. uneven mounting can ca use the dbc substrate of package to be damaged. the pre-screwing torque is set to 20 ~ 30% of maximum torque rating. parameter conditions limits unit min. typ. max. device flatness see figure 9 0 - +150 ? m mounting torque mounting screw: m3 see figure 10 recommended 0.7 n m 0.6 0.7 0.8 n m recommended 7.1 kg cm 6.2 7.1 8.1 kg cm terminal pulling strength load 19.6 n 10 - - s terminal bending strength load 9.8 n, 90 deg. bend 2 - - times weight -1 5-g ( + ) ( + ) ( + ) ( + ) 1 2 pre - screwing : 1 2 final screwing : 2 1
?2016 fairchild semiconductor corporation 11 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series time charts of spms protective function figure 11. under-voltage protection (low-side) a1 : control supply voltage rises: after the voltage rises uv ddr , the circuits start to operate when next input is applied. a2 : normal operation: igbt on and carrying current. a3 : under voltage detection (uv ddd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts with a fixed pulse width. a6 : under voltage reset (uv ddr ). a7 : normal operation: igbt on and carrying curr ent by triggering next signal from low to high. figure 12. under-voltage protection (high-side) b1 : control supply voltage rises: after the voltage reaches uv bsr , the circuits start to operate when next input is applied. b2 : normal operation: igbt on and carrying current. b3 : under voltage detection (uv bsd ). b4 : igbt off in spite of control input c ondition, but there is no fault output signal. b5 : under voltage reset (uv bsr ). b6 : normal operation: igbt on and carrying curr ent by triggering next signal from low to high. input signal output current fault output signal control supply voltage reset uv ddr protection circuit state set reset uv ddd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output)
?2016 fairchild semiconductor corporation 12 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series figure 13. short-circui t current protection (low-side operation only) (with the external sense resistance and rc filter connection) c1 : normal operation: igbt on and carrying current. c2 : short circuit current detection (sc trigger). c3 : all low-side igbts gate are hard interrupted. c4 : all low-side igbts turn off. c5 : fault output operation starts with a fixed pulse width. c6 : input high: igbt on state, but during the acti ve period of fault output the igbt doesnt turn on. c7 : fault output operation finishes, but igbt doesnt turn on until trig gering next signal from low to high. c8 : normal operation: igbt on and carrying current. input/output interface circuit figure 14. recommended cpu i/o interface circuit note: 13. rc coupling at each input might change depending on the pwm control scheme used in the appli cation and the wiring impedance of the applications printed circuit board. the input signal section of the motion spm 3 product integrates 5 k ?? ( typ.) pull-down resistor. therefore, when using an external filtering resistor, please pay attention to the sig- nal voltage drop at input terminal. lower arms control input output current sensing voltage of sense resistor fault output signal sc reference voltage rc filter circuit time constant delay sc current trip level protection circuit state set reset c6 c7 c3 c2 c1 c8 c4 c5 internal igbt gate-emitter voltage internal delay at protection circuit mcu com +5v (mcu or control power ) ,, in (u l) in (vl) in (wl) ,, in (uh) in (vh) in (w h ) v fo 4.7 k ? spm
?2016 fairchild semiconductor corporation 13 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series figure 15. typical application circuit note: 14. to avoid malfunction, the wiring of each input should be as short as possible. (less than 2 - 3 cm) 15. v fo output is open-drain type. this signal line should be pulled up to the positive side of the m cu or control power supply with a resistor that makes i fo up to 2 ma. please refer to figure 14. 16. input signal is active-high type. there is a 5 k ? resistor inside the ic to pull-down each input signal line to gnd. rc coupling circuits should be adopted for the prevention of input signal oscillation. r 1 c 1 time constant should be selected in the range 50 ~ 150 ns . ( recommended r 1 = 100 ? , c 1 = 1 nf) 17. each wiring pattern inductance of a point should be minimized (recommend less than 10 nh). use the shunt resistor r 4 of surface mounted (smd) type to reduce wiring inductance. to prevent malfunction, wiring of point e should be connected to the terminal of the shu nt resistor r 4 as close as possible. 18. to prevent errors of the protection function, the wiri ng of b, c, and d point should be as short as possible. 19. in the short-circuit protection circuit, please select the r 6 c 6 time constant in the range 1.5 ~ 2 ? s. do enough evaluaiton on the real system because shor t-circuit protection time may vary wiring pattern layout and value of the r 6 c 6 time constant. 20. each capacitor should be mounted as close to the pins of the motion spm ? 3 product as possible. 21. to prevent surge destruction, the wiring between the smoothing capacitor c 7 and the p & gnd pins should be as short as possible. the use of a high-frequency non-inductive capacitor of around 0.1 ~ 0.22 ? f between the p & gnd pins is recommended. 22. relays are used at almost every systems of electrical equipments at industrial application. in these cases, there should b e sufficient distance between the cpu and the relays. 23. the zener diode or transient voltage suppressor should be adopted for the protection of ics from the surge dest ruction betw een each pair of control supply terminals (recommanded zener diode is 22 v / 1 w, which has the lower zener impedance characteristic than abou t 15 ? ). 24. c 2 of around 7 times larger than bootstrap capacitor c 3 is recommended. 25. please choose the electrolytic capacitor with good temperature characteristic in c 3 . also, choose 0.1 ~ 0.2 ? f r-category ceramic capacitors with good temperature and frequency characteristics in c 4 . fault c 3 c 4 c 2 c 4 5v line r 3 c 1 r 1 m v dc c 7 gating uh gating vh gating wh gating wl gating vl gating ul c 1 m cu r 5 r 5 r 5 r 4 r 4 r 4 c 5 c 5 c 5 w-phase current v-phase current u-phase current r 6 com v dd in in in v fo v ts c sc out out out n u (21) n v (22) n w (23) u (24) v (25) w (26) p (27) (20) v s(w) (19) v b(w) (16) v s(v) (15) v b(v) (8) c sc (7) v ts (6) v fo (5) in (wl) (4) in (vl) (3) in (ul) (2) com (1) v dd(l) v dd v b out com v s in (18) v dd(h) (17) in (wh) (14) v dd(h) (13) in (vh) (12) v s(u) (11) v b(u) (10) v dd(h) (9) in (uh) input signal for short-circuit protection c 6 r 1 r 1 r 1 r 1 r 1 r 1 c 1 c 1 c 1 a b d c e v dd v b out com v s in v dd v b out com v s in c 3 c 4 c 3 c 4 15v line c 4 c 4 c 4 c 1 c 1 c 1 d 2 d 2 d 2 power gnd line control gnd line d 2 vts c 5
?2016 fairchild semiconductor corporation 14 www.fairchildsemi.com FNB33060T rev. 1.1 FNB33060T motion spm 3 ? series detailed package outline drawings (FNB33060T) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or data on the drawing and contact a fairchildsemicondu ctor representative to veri fy or obtain the most recent revision. package s pecifications do not expand the terms of fa irchilds worldwide therm and conditions, specifically the the warranty therei n, which covers fairchild products. always visit fairchild semiconduct ors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/mo/mod27ba.pdf
?2016 fairchild semiconductor corporation 15 www.fairchildsemi.com FNB33060T rev. 1.1
www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including typic als must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your localsales representative ? semiconductor components industries, llc

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